1. Field of the Invention
The present invention relates to an array substrate for a display device, and more particularly, to an array substrate including a thin film transistor and a storage capacitor and a method of fabricating the array substrate.
2. Discussion of the Related Art
As information technology progresses, flat panel display (FPD) devices having light weight, thin profile and low power consumption have been developed. Specifically, a cathode ray tube (CRT) has been replaced by the FPD devices such as a liquid crystal display (LCD) device or an organic electroluminescent display (ELD) device.
The LCD devices use the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Among various types LCD devices, an active matrix type liquid crystal display (AM-LCD) device where a thin film transistor (TFT) is formed in each pixel region as a switching element turning on/off a voltage has been the subject of recent research due to its high resolution and superior quality for displaying moving images.
The organic ELD devices have a high brightness and a low driving voltage. In addition, since the organic ELD devices are an emissive type, the organic ELD devices have a high contrast ratio and a thin profile. Also, the organic ELD devices can display images without viewing angle limitations. Further, since the organic ELD devices have a short response time of several microseconds (μs), the organic ELD devices have a stable operation property at a low temperature and an advantage in displaying moving images. Moreover, since the organic ELD devices are driven with a relatively low voltage of about 5 V to about 15 V, the organic ELD devices have advantages in design and fabrication of a driving circuit.
Each of an AM-LCD device and an organic ELD device includes an array substrate having a thin film transistor (TFT) in each pixel region as a switching element for controlling a data signal application. Specifically, the array substrate of the organic ELD device further has a driving TFT for driving an organic electroluminescent (EL) diode in each pixel region.
FIG. 1 is a cross-sectional view showing an array substrate for a display device according to the related art. In FIG. 1, a gate electrode 15 and a gate line (not shown) are formed on a substrate 11 having a pixel region P, and a gate insulating layer 18 is formed on the gate electrode 15 and the gate line. A semiconductor layer 28 including an active layer 22 of intrinsic amorphous silicon and an ohmic contact layer 26 of impurity-doped amorphous silicon is formed on the gate insulating layer 18 over the gate electrode 15. In addition, source and drain electrodes 36 and 38 spaced apart from each other are formed on the ohmic contact layer 26, and a data line 33 is formed over the gate insulating layer 18. A semiconductor pattern 29 including first and second patterns 27 and 23 is formed between the data line 33 and the gate insulating layer 18.
The gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, the source electrode 36 and the drain electrode 38 constitute a thin film transistor (TFT) Tr. When the display device is an organic electroluminescent display device, the TFT Tr may function as a driving TFT, and a switching TFT (not shown) connected to the gate line, the data line 33 and the TFT Tr may be formed in the pixel region P. Further, a passivation layer 42 is formed on the source and drain electrodes 36 and 38, and a pixel electrode 50 is formed on the passivation layer 42 in the pixel region P. The passivation layer 42 includes a drain contact hole 45 exposing the drain electrode 38, and the pixel electrode 50 is connected to the drain electrode 38 through the drain contact hole 45.
In the TFT Tr, the active layer 22 of the semiconductor layer 28 includes a first portion exposed between the ohmic contact layer 26 and a second portion under the ohmic contact layer 26. The first portion of the active layer 22 has a first thickness t1 and the second portion of the active layer 22 has a second thickness t2 different from the first thickness t2 (t1≠t2). The difference between the first and second thicknesses t1 and t2 cause deterioration of the TFT Tr.
FIG. 2 is a cross-sectional showing a step of forming a semiconductor layer, a source electrode and a drain electrode of an array substrate for a display device according to the related art. Although not shown in FIG. 2, an active layer, an impurity-doped amorphous silicon pattern and a source-drain pattern are formed on a substrate 11 by patterning an intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer and a metal layer. Next, source and drain electrodes 36 and 38 are formed by patterning the source-drain pattern, and the impurity-doped amorphous silicon pattern is exposed between the source and drain electrodes 36 and 38.
In FIG. 2, the impurity-doped amorphous silicon pattern exposed between the source and drain electrodes 36 and 38 is removed by a dry etching method to form an ohmic contact layer 26 under the source and drain electrodes 36 and 38. When the dry etching step is performed for a insufficient time, the impurity-doped amorphous silicon pattern exposed between the source and drain electrodes 36 and 38 may remain on the active layer 26 and the remaining impurity-doped amorphous silicon pattern may deteriorate a thin film transistor (TFT) Tr (of FIG. 1). Accordingly, the dry etching step is performed for a sufficient time to remove the impurity-doped amorphous silicon pattern exposed between the source and drain electrodes 36 and 38 completely and the active layer 22 under the impurity-doped amorphous silicon pattern is partially removed. As a result, the active layer 22 includes a first portion that is exposed between the source and drain electrodes 36 and 38 and has a first thickness t1 and a second portion that is under the ohmic contact layer 26 and has a second thickness t2 different from the first thickness (t1≠t2).
However, the thickness difference between the first and second portions of the active layer 22 deteriorates the TFT Tr. In addition, since the intrinsic amorphous silicon layer is formed to have a sufficient thickness over about 1000 Å based on the partial removal of the active layer 22 in the dry etching step, the deposition time for the intrinsic amorphous silicon layer increases and productivity is reduced.
In an array substrate for a display device such as an AM-LCD device and an organic ELD device, a thin film transistor (TFT) is connected to a gate line, a data line and a pixel electrode in each pixel region and applies a data signal to the pixel electrode selectively and periodically. The TFT includes an active layer and the active layer may be formed of amorphous silicon or polycrystalline silicon. Since amorphous silicon has a random atomic arrangement, amorphous silicon has a transition from a stable state to a quasi-stable state when light is irradiated or when an electric field is applied. Accordingly, the TFT including an active layer of amorphous silicon has problems in stability. In addition, since amorphous silicon has relatively low carrier mobility within a range of about 0.1 cm2/Vs to about 1.0 cm2/Vs in a channel region, the TFT including an active layer of amorphous silicon has problems in use as an element of a driving circuit.
To solve the above problems of amorphous silicon, the TFT including an active layer of polycrystalline silicon has been suggested. For example, amorphous silicon for a semiconductor layer may be crystallized to become polycrystalline by a crystallization method using a laser apparatus.
FIG. 3 is a cross-sectional view showing an array substrate including a polycrystalline silicon thin film transistor according to the related art. In FIG. 3, a buffer layer 53 is formed on a substrate 51, and a semiconductor layer 55 of polycrystalline silicon is formed on the buffer layer 53. The semiconductor layer 55 includes an active region 55a of intrinsic polycrystalline silicon and a source-drain region 55b of impurity-doped polycrystalline silicon at both sides of the active region 55a. The source-drain region 55b may include one of negative type impurities of high concentration (n+) and positive type impurities of high concentration (p+).
A gate insulating layer 58 is formed on the semiconductor layer 55, and a gate electrode 59 is formed on the gate insulating layer 58 over the semiconductor layer 55. In addition, an interlayer insulating layer 61 is formed on the gate electrode 59, and source and drain electrodes 70 and 72 are formed on the interlayer insulating layer 61. The interlayer insulating layer 61 and the gate insulating layer 58 include first and second semiconductor contact holes 63 and 64 exposing the source-drain region 55b, and the source and drain electrodes 70 and 72 are connected to the source-drain region 55b through the first and second semiconductor contact holes 63 and 64, respectively. A passivation layer 75 is formed on the source and drain electrodes 70 and 72, and a pixel electrode 82 is formed on the passivation layer 75. The passivation layer 75 includes a drain contact hole 78 exposing the drain electrode 72, and the pixel electrode 82 is connected to the drain electrode 78 through the drain contact hole 78.
The source-drain region 55b may be formed by doping the semiconductor layer of intrinsic polycrystalline silicon with the impurities, and the doping step may be performed using an ion implantation apparatus. Accordingly, an additional apparatus is required for fabricating a polycrystalline silicon TFT and fabrication cost increases.
Further, when a bottom gate structure where a gate electrode is under a semiconductor layer is applied to a polycrystalline silicon TFT, a crystallization step having a relatively high process temperature is performed for a semiconductor layer of amorphous silicon over a gate electrode. Since the gate electrode is formed of a metallic material, the gate electrode may be degraded during the crystallization step.
Moreover, as a display device having higher quality and higher resolution is required, a size of a pixel region is reduced. As a result, a sufficient capacitance of a storage capacitor without reduction of aperture ratio has been the subject of recent research and development.